1. Field of the Invention
The present invention relates to a semiconductor memory, and more specifically, it relates to a nonvolatile semiconductor memory.
2. Description of the Background Art
A nonvolatile semiconductor memory such as an EPROM (erasable and programmable read only memory) or an EEPROM (electrically erasable and programmable read only memory) has recently been watched with interest as a semiconductor memory substitutional for a magnetic memory such as a hard disk or a floppy disk.
A memory cell of an EPROM or an EEPROM stores carriers in a floating gate electrode for storing data in response to presence/absence of the carriers and reading the data by detecting change of a threshold voltage responsive to presence/absence of the carriers. In particular, the EEPROM includes a flash EEPROM erasing data in the overall memory cell array or dividing the memory cell array into arbitrary blocks and erasing data in units of the blocks. This flash EEPROM, also referred to as a flash memory, can attain a large capacity, low power consumption and a high-speed operation, and is excellent in shock resistance. Therefore, the flash EEPROM is used in various portable devices. Further, memory cells of the flash EEPROM can advantageously be more easily integrated as compared with those of the EEPROM.
In general, a stacked gate memory cell and a split gate memory cell are proposed as memory cells forming a flash EEPROM.
In a write operation of storing electrons in a floating gate of a stacked gate memory cell, electrons stored in a channel of a semiconductor substrate are converted to hot electrons, which in turn are injected into the floating gate electrode. At this time, a voltage of 10-odd V to a control gate electrode. In an erase operation of extracting electrons stored in the floating gate electrode of the stacked gate memory cell, a Fowler-Nordheim tunnel current (hereinafter referred to as an F-N tunnel current) is fed from a source region to the floating gate electrode. At this time, a voltage of 10-odd V must be applied to the source region.
In a write operation of storing electrons in a floating gate electrode of the split gate memory cell, electrons stored in a channel of a semiconductor substrate are converted to hot electrons, which in turn are injected into the floating gate electrode. At this time, a voltage of 10-odd V must be applied to a source region. In an erase operation of extracting electrons from the floating gate electrode of the stacked gate memory cell, an F-N tunnel current is fed from a control gate electrode to the floating gate electrode. At this time, a voltage of 10-odd V must be applied to the control gate electrode.
Thus, hot electrons are employed for injecting electrons into the floating gate electrode in the write operation and the F-N tunnel current is employed for extracting the electrons stored in the floating gate electrode in the erase operation in the conventional stacked or split gate memory cell.
In order to hold the carriers stored in the floating gate electrode over a long period, the thickness of an insulator film enclosing the floating gate electrode must be increased. However, the hot electrons or the F-N current is utilized for injecting or extracting the electrons into or from the floating gate electrode. Therefore, the voltage (hereinafter referred to as an operating voltage for the memory cell) applied to the control gate electrode or the drain region in the write or erase operation must be increased as the thickness of the insulator film enclosing the floating gate electrode is increased.
The operating voltage for the memory cell is generated in a step-up circuit. In this case, a practical voltage is up to 10-odd V. When a silicon oxide film is employed as the insulator film enclosing the floating gate electrode and the operating voltage for the memory cell is set to 10-odd V, however, it is difficult to increase the thickness of the silicon oxide film beyond 10 nm. In general, therefore, the thickness of the silicon oxide film employed as the insulator film enclosing the floating gate electrode is set to not more than 10-odd nm, in order to suppress the operating voltage for the memory cell to 10-odd V. It is known that the electrons stored in the floating gate electrode can be held for a period practically satisfiable to some extent if the thickness of the silicon oxide film is at least 8 nm.
Also when holes are stored in the floating gate electrode, the thickness of the silicon oxide film employed as the insulator film enclosing the floating gate electrode is set to not more than 10-odd nm thereby suppressing the operating voltage for the memory cell to not more than 10-odd V while holding the holes stored in the floating gate electrode for a period practically satisfiable to some extent, similarly to the aforementioned case of storing electrons.
The flash EEPROM is recently required to attain a lower voltage, a higher operating speed, lower power consumption and higher integration while ensuring a sufficiently long holding time (at least 10 years) for carriers stored in the floating gate electrode.
As hereinabove described, the thickness of the silicon oxide film must not be reduced below 8 nm in general, in order to ensure a carrier holding time of at least 10 years when employing the silicon oxide film as the insulator film enclosing the floating gate electrode.
When the operating voltage for the memory cell is reduced, the step-up time (lead time) can be reduced for increasing the speed for a write operation and an erase operation. Further, power consumption can also be reduced.
The circuit scale of the step-up circuit for generating the operating voltage for the memory cell is increased as the level of the generated voltage is increased. An area (transistor size) of a substrate occupied by a transistor forming a peripheral circuit (a decoder, a sense amplifier, a buffer or the like) for the flash EEPROM is increased as the withstand voltage is increased. When the operating voltage for the memory cell is reduced, therefore, the circuit scale of the step-up circuit as well as the size of the transistor forming the step-up circuit are reduced, whereby higher integration can be attained.
Therefore, a high-speed operation, low power consumption and high integration can be simultaneously implemented by reducing the operating voltage for the memory cell.
Also generally known is a split gate flash EEPROM capacitively coupling a source diffusion layer with a floating gate thereby controlling the potential of the floating gate by the potential of the source diffusion layer. According to this structure, the source diffusion layer is capacitively coupled with the floating gate, while a control gate is also capacitively coupled with the floating gate. In this case, the control gate covers the upper portion and the side surface of the floating gate in the structure of the conventional split gate flash EEPROM, leading to large opposite areas of the control gate and the floating gate. Therefore, the coupling ratio between the control gate and the floating gate is increased to some extent. Thus, the coupling ratio between the source diffusion layer and the control gate is relatively reduced, and hence a high voltage must be applied to the source diffusion layer in order to control the potential of the floating gate by the potential of the source diffusion layer. Consequently, it is difficult to reduce the operating voltage in the conventional split gate flash EEPROM controlling the potential of the floating gate by the potential of the source diffusion layer.
An object of the present invention is to provide a semiconductor memory capable of achieving a high-speed operation, low power consumption and high integration by increasing the life of the semiconductor memory and reducing the voltage therefor.
Another object of the present invention is to increase the coupling ratio between a diffusion layer and a floating gate by reducing the coupling ratio between the floating gate and a control gate in the aforementioned semiconductor memory.
A semiconductor memory according to an aspect of the present invention comprises a floating gate, a first diffusion layer capacitively coupled with the floating gate for controlling the potential of the floating gate and a control gate arranged oppositely to the floating gate. In an erase operation, the control gate feeds a tunnel current to the floating gate in a direction substantially parallel to the main surface of a semiconductor substrate. Throughout the specification, the term xe2x80x9cdiffusion layerxe2x80x9d indicates an impurity region or the like formed on the surface of a semiconductor substrate. The term xe2x80x9csemiconductor substratexe2x80x9d indicates a wide concept including not only a general semiconductor substrate but also a semiconductor layer formed on an insulated substrate.
The semiconductor memory according to this aspect is so formed that the control gate feeds the tunnel current to the floating gate in the direction substantially parallel to the main surface of the semiconductor substrate in the erase operation as hereinabove described, whereby the tunnel current can be fed by extracting carriers from the floating gate also when the control gate has no region overlapping with the upper portion of the control gate. Thus, the capacitance between the floating gate and the control gate can be reduced as compared with a structure having a control gate overlapping with the upper portion of a floating gate. Therefore, the coupling ratio between the floating gate and the control gate is reduced, whereby the coupling ratio between the first diffusion layer and the floating gate is increased. Also when a voltage lower than that in the structure having the control gate overlapping with the upper portion of the floating gate is applied to the first diffusion layer, therefore, the potential of the floating gate can be so easily increased that writing can be performed with a low voltage. Further, the step-up time is reduced due to the reduction of the voltage, thereby enabling high-speed writing. In addition, potential difference can be easily attained between the control gate and the floating gate in erasing, whereby sufficient erasing can be performed with a control gate voltage lower than that in the prior art.
In the semiconductor memory according to the aforementioned aspect, the floating gate preferably has an acute forward end in a direction substantially parallel to the main surface of the semiconductor substrate in a portion opposite to the control gate. According to this structure, an electric field can be concentrated to the acute forward end, whereby carriers can be extracted from the floating gate also when a voltage applied to the control gate in erasing is lower than that applied in a case where the floating gate has no acute forward end. Thus, erasing can be performed with a low voltage. Further, a step-up time is reduced due to the reduction of the voltage, thereby enabling high-speed erasing. In addition, the coupling ratio between the floating gate and the control gate is further reduced due to the acute forward end, thereby further increasing the coupling ratio between the first diffusion layer and the floating gate. Thus, the potential of the floating gate can be easily increased also when a voltage lower than that in a structure having no acute shape is applied to the diffusion layer, thereby enabling high-speed writing.
In the semiconductor memory including the floating gate having the aforementioned acute forward end, the acute forward end of the floating gate is preferably formed by isotropic etching. According to this structure, the floating gate can be easily formed with the acute forward end.
In the semiconductor memory including the floating gate having the aforementioned acute forward end, the acute forward end of the floating gate may be located around the lower surface of a side of the floating gate closer to the control gate. The semiconductor memory may further comprise a tunnel insulator film formed between the acute forward end of the floating gate and a portion of the control gate opposite to the acute forward end of the floating gate. Further, a side surface of the floating gate including the acute forward end may be concavely formed. In addition, a portion of the control gate opposite to the acute forward end of the floating gate may be concavely formed.
In the semiconductor memory including the floating gate having the aforementioned acute forward end, the control gate is preferably formed not to overlap with at least a portion of the floating gate other than the acute forward end. According to this structure, the coupling ratio between the control gate and the floating gate can be easily reduced, thereby increasing the coupling ratio between the first diffusion layer and the floating gate.
In the semiconductor memory including the floating gate having the aforementioned acute forward end, a portion of the floating gate other than the acute forward end preferably has a thickness of not more than 50 nm. When the floating gate is formed with such a small thickness, the area of a portion of the floating gate opposite to the control gate is so reduced that the coupling ratio between the floating gate and the control gate can be reduced. Thus, the coupling ratio between the floating gate and the first diffusion layer is increased, whereby writing can be easily performed also when the voltage applied to the first diffusion layer is reduced. Thus, a high-speed operation, low power consumption and high integration can be attained by reducing the voltage.
In the semiconductor memory according to the aforementioned aspect, the floating gate preferably has a thickness of not more than 50 nm. When the floating gate is formed with the extremely small thickness of not more than 50 nm, the overall floating gate can be acutely formed and may not have the acute forward end.
In the semiconductor memory according to the aforementioned aspect, the control gate is preferably formed on the semiconductor substrate through a first insulator film, and an upper surface portion of the semiconductor substrate formed with the first insulator film is preferably dug down beyond an upper surface portion of the semiconductor substrate formed with the floating gate by at least the thickness of the first insulator film and not more than the mean free path of electrons. According to this structure, the side surface, closer to the floating gate, of the control gate substantially perpendicular to the main surface of the semiconductor substrate can reliably cover the acute forward end of the floating gate as a counter electrode. Thus, the voltage applied to the control gate can be further reduced in erasing. When the surface portion of the semiconductor substrate is dug down by the depth not more than the mean free path of electrons, probabilities of generation and injection of hot electrons employed for writing can be prevented from reduction. In this case, the lower surface of the control gate is preferably located downward beyond the lower surface of the floating gate.
In the semiconductor memory according to the aforementioned aspect, the control gate may be formed on the semiconductor substrate through a first insulator film having a first thickness, and the floating gate may be formed on the semiconductor substrate through a second insulator film having a second thickness smaller than the first thickness.
In the semiconductor memory according to the aforementioned aspect, the length of overlapping portions of the floating gate and the first diffusion layer along the gate length direction is preferably not more than half the length of the floating gate along the gate length direction. In the semiconductor memory according to the aforementioned aspect, the coupling ratio between the floating gate and the control gate is so extremely reduced that a sufficiently high coupling ratio can be obtained between the floating gate and the first diffusion layer also when the first diffusion layer capacitively coupled with the floating gate is overlapped with the floating gate by the length not more than half the length of the floating gate along the gate length direction. Therefore, the potential of the floating gate can be controlled in the small voltage range of the first diffusion layer. When the overlapping length of the floating gate and the first diffusion layer is reduced, the distance between the first diffusion layer (source diffusion layer) and a drain diffusion layer is increased beyond that in the prior art, and hence the lengths of the floating gate and the control gate can be reduced thereby easily attaining refinement and a high-speed operation.
In this case, the length of overlapping portions of the floating gate and the first diffusion layer along the gate length direction may be not more than one third of the length of the floating gate along the gate length direction. Further, the coupling ratio between the floating gate and the first diffusion layer is preferably greater than the coupling ratio between the floating gate and the control gate.
The semiconductor memory according to the aforementioned aspect may further comprise a second diffusion layer formed on the main surface of the semiconductor substrate at a prescribed space from the first diffusion layer, and the control gate and the floating gate may be arranged between the first diffusion layer and the second diffusion layer at a prescribed space along a direction parallel to the main surface of the semiconductor substrate.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.